in short
Nvidia has locked up more than half of TSMC's total advanced packaging capacity through 2027. High-bandwidth memory is effectively sold out for 2026 and much of 2027. A new fab, from groundbreaking to volume output, takes three to five years — regardless of how much capital gets thrown at it. Efficiency and pricing can move as fast as software allows. The factory floor still runs on the physics of concrete curing and cleanroom certification, and it does not care how exponential the demand curve looks.
The now-familiar story about AI economics goes like this: prices fall, efficiency rises, and usage grows fast enough to swallow the savings whole — the Jevons paradox, playing out in real time. That story is true, and it explains why total spending keeps climbing even as the cost per unit of intelligence collapses. But it describes the financial side of the bottleneck. Underneath the pricing story sits a physical one, and it’s arguably tighter: the actual hardware — the packaged, memory-equipped chip that turns electricity into inference — is gated by manufacturing capacity that expands on a timeline measured in years, while demand for it compounds on a timeline measured in quarters. Price and efficiency are software problems. Fabrication and packaging are civil engineering problems. They do not move at the same speed, and right now the gap between them is the real constraint on how much AI the world can actually build.
The Bottleneck Moved — From the Transistor to the Package
For decades, the standard chokepoint in chip manufacturing was shrinking the transistor: get more of them onto a wafer, and yields determined how much useful silicon came out the other end. That’s no longer where the AI hardware supply chain actually breaks. Foundries can produce advanced-node logic dies at high yield today. What they can’t do fast enough is package those dies together with the high-bandwidth memory an AI accelerator needs to function — a process called CoWoS (chip-on-wafer-on-substrate), and it is now, by wide consensus across TSMC’s own earnings commentary and independent supply-chain analysts, the single tightest link in the entire AI hardware chain (SupplyICs; Absolute Digital Publishers).
The numbers illustrate why. TSMC has been racing to expand CoWoS output — from roughly 35,000 wafers per month in late 2024 toward a targeted 130,000 by the end of 2026, nearly a fourfold increase in under two years (Oplexa; Troy Technical). That is one of the fastest capacity expansions in the history of the semiconductor industry. It is still not enough. Both of TSMC’s advanced packaging families were fully booked as of late 2025, with lead times running 52 to 78 weeks — over a year just to get in line (SiliconAnalysts). Nvidia alone has secured more than half of TSMC’s total advanced packaging allocation through at least 2027, meaning every competing AI hardware program — AMD, custom hyperscaler silicon, anyone else who wants an accelerator built — is queuing behind that reservation (ai|expert; NextWaves Insight).
Memory Has Its Own, Separate Shortage
Even a chip that clears the packaging queue still needs high-bandwidth memory, and that market is arguably tighter than packaging. HBM3E is effectively sold out through 2026; Micron has reportedly sold its entire 2026 HBM supply in advance, locking in the revenue before the product exists (SiliconAnalysts; ENKI). IDC has gone so far as to classify the shortage as a potentially permanent structural reallocation of global silicon wafer capacity toward AI memory, rather than an ordinary cyclical shortage that resolves once new supply comes online — a distinction that matters, because it implies the tightness isn’t a temporary phase to wait out (Barrack AI).
The reason is a matter of physics, not corporate strategy: each gigabyte of HBM consumes three to four times the wafer capacity of standard DRAM (Barrack AI). Every gigabyte hyperscalers pull toward AI accelerators is capacity pulled directly away from ordinary consumer memory — which is why DRAM prices have moved in lockstep with the AI buildout, up 30 to 55% in a single quarter by some estimates, even though the shortage is fundamentally about servers, not laptops (Investing.com; GPUnex). Consumer electronics manufacturers are now competing with hyperscalers for the same finite wafer capacity, and losing.
Why Capital Can't Buy Its Way Out of This
Here is the part that separates a physical bottleneck from a financial one: this problem does not respond to money the way a pricing problem does. A new fab costs $10–20 billion and takes three to five years from groundbreaking to meaningful volume — eighteen months of physical construction, another twelve to eighteen months of cleanroom certification and tool installation, then a further ramp-up period before yields reach commercial levels (SupplyICs; Investing.com). Every major memory maker is now investing at a historic pace — combined HBM-related capital commitments across the three leading suppliers exceed $50 billion — and even that scale of spending will not produce meaningful new volume before late 2027 or 2028 (GPUnex; Barrack AI). Intel’s own CEO has said plainly that there is no relief before 2028.
This is the mechanism that makes the underlying intuition correct: price can fall, efficiency can rise, and none of it moves the completion date of a fab under construction. Capital intensity and construction physics set a floor under how fast supply can grow, full stop — and demand, driven by a genuinely exponential usage curve, is growing faster than that floor allows. The result is not a temporary shortage that resolves itself. It’s a structural mismatch between two curves with fundamentally different speed limits.
The Challenge: Isn't This Just How Every Capacity Cycle Looks From the Inside?
The honest counter-argument deserves real weight. Every semiconductor upcycle in history has looked exactly like this from the inside — acute shortages, capital flooding in, breathless warnings that “this time is structural” — and every one of them has eventually resolved as new capacity came online and demand growth normalized. Fabs are being built right now, at record pace and record spend; treating the current tightness as permanent risks repeating the same mistake previous cycles made in the opposite direction, assuming a temporary squeeze was a permanent ceiling.
There’s a reasonable rebuttal to that rebuttal, though, and it’s worth stating plainly rather than resolving falsely: IDC’s “permanent reallocation” framing is not simply repeating the standard cyclical narrative — it’s specifically arguing that AI memory demand is large and price-inelastic enough (a projected 70% of global memory production by 2026, per one estimate) that it structurally changes production economics rather than just straining them temporarily (ENKI). Whether that argument holds is a genuinely open question. What isn’t open to argument is the physics: fab construction and CoWoS qualification take years regardless of which side of that debate turns out to be right, and no amount of capital compresses that timeline meaningfully.
Conclusion
The Jevons story explains why AI spending keeps rising even as prices fall. This is the story underneath it: the reason hardware itself stays intensive — expensive, scarce, backlogged — isn’t that manufacturers won’t build more. It’s that they physically can’t build it fast enough, on any timeline shorter than years, to keep pace with a usage curve moving in quarters. Software efficiency is elastic. Concrete, cleanrooms, and packaging queues are not. That mismatch, more than any pricing dynamic, is the real ceiling on how much AI the world can build in this decade.
source
covers
CoWoS as the binding constraint, not wafer fabrication
TSMC Q2 2026 earnings framing
CoWoS capacity expansion trajectory
CoWoS sold out through 2026; ABF substrate shortage
CoWoS lead times; HBM3E/HBM4 allocation
Nvidia’s packaging allocation share
Nvidia CoWoS reservation through 2027
HBM wafer intensity; IDC “permanent reallocation” framing
AI’s projected 70% share of global memory production
Fab construction cost/timeline; DRAM price impact
Combined HBM capex; fab lead-time detail
Phase-by-phase fab construction timeline
